The present invention relates to electrically erasable and programmable memories, and more particularly to page-erasable FLASH memories.
Currently, the market of electrically erasable and programmable memories in integrated circuits mainly comprises EEPROM memories and FLASH memories (or FLASH-EEPROM). EEPROM memories can be word programmable and erasable or page programmable and erasable. For technological reasons, FLASH memories (or FLASH-EEPROM) are generally word programmable and sector erasable, one sector generally comprising many pages.
As background, FIG. 1 schematically represents a FLASH memory array comprising a plurality of memory cells CFi,j arranged as a matrix and connected to word lines WLi and bit lines BLj. The cells CFi,j of the FLASH memory are very simple in structure and only comprise one floating-gate transistor FGT, here an NMOS transistor, having its gate G connected to a word line WLi, its drain D connected to a bit line BLj and its source S connected to a source line SLi. The bit lines BLj are grouped together by columns of rank k to form binary words Wi,k comprising for example eight cells CFi,j each (bytes), the cells of a single word Wi,k possibly being adjacent (as represented in FIG. 1) or interlaced with cells belonging to other words. A physical page Pi of the FLASH memory is formed by all the memory cells Ci,j connected to a single word line WLi, and thus comprises a plurality of binary words Wi,k. A sector is formed by a set of pages Pi the source lines SLi of which are interconnected and are always at the same electric potential.
In such a FLASH memory, the programming of a cell involves injecting electric charges into the floating gate by hot electron injection effect while the erasing of a cell involves extracting electric charges trapped in the floating gate by tunnel effect. An erased transistor FGT has a positive threshold voltage VT1 of low value and a programmed transistor has a threshold voltage VT2 higher than VT1. When a read voltage VREAD that is between VT1 and VT2 is applied to its gate, an erased transistor is on, which corresponds by convention to the reading of a logic xe2x80x9c1xe2x80x9d, and a programmed transistor remains off, which corresponds by convention to the reading of a logic xe2x80x9c0xe2x80x9d.
Due to the simplicity of their memory cells, which do not comprise access transistors as in EEPROM memories, FLASH memories have the advantage of being very compact in terms of silicon surface occupied and therefore have, for a constant silicon surface, a storage capacity that is much greater than that of EEPROM memories, for a lower cost price. However, they are less flexible to use due to the need to simultaneously erase all the memory cells of a single sector.
In certain applications, it is however desirable to benefit from the advantages of FLASH memories (compactness and cost price) while benefiting from the possibility of erasing by page, for example when the data to be logged are small in volume and the erasure of an entire sector before programming a page cannot be considered. However, finding a page-erasable FLASH memory involves certain difficulties.
To understand the problem posed, it will first be reminded that a memory cell can be erased according to the source erase method or the channel erase method. The source erase method, referring to FIG. 1, involves applying a positive erase voltage VER+ in the order of 4 to 5V to all the source lines SLi of a single sector, while the word lines WLi of the sector considered receive a negative erase voltage VERxe2x88x92 in the order of xe2x88x928V, the material forming the channel of the transistors (substrate or well) being grounded. The effect of the difference in potential appearing between the source S and the gate G of the transistors is to force out the electric charges trapped in the floating gates (by tunnel effect) and to erase the transistors. The negative voltage VERxe2x88x92 is applied to the gates of all the transistors of a single sector by inhibiting a word line decoder XDEC (FIG. 1), which receives the voltage VERxe2x88x92 at one input and applies it to all the word lines WLi of the sector to be erased regardless of the address received at input. Simultaneously, all the outputs of a column decoder YDEC connected to the bit lines BLj are taken to high impedance.
The channel erase method can be distinguished from the source erase method by the fact that the positive erase voltage VER+ is applied to the sources of the transistors through the material forming the channel regions (substrate or well) to which a bias voltage VB is applied. The junctions PN existing between the channel regions and the source regions are biased in the forward direction and the voltage VB is passed onto all the sources of the transistors of a single sector to form the voltage VER+. At the same time, the negative erase voltage VERxe2x88x92 is, as above, applied to the gates of the transistors through the word line decoder XDEC that is in the inhibited state.
The advantage of a channel erase method is that the channel regions and the source regions are at substantially the same electric potential, the channel/source junction diodes being biased in the forward direction. Compared to a source erase method, there is therefore no longer any leakage current in the source/channel direction. The erase voltage VER+ can be taken to a higher potential than in the case of a source erase method, such as 8 to 10V for example against 4 to 5V in the first case.
One known approach for producing a page-erasable FLASH memory involves equipping each source line SLi with a select transistor allowing for a selective application of the erase voltage VER+. This approach is in accordance with the teaching disclosed by the patent EP 704 851 and the application WO 98/33187, in which the selective erasure of a word is obtained by equipping the cells of a single word with a source select transistor.
However, this approach has various disadvantages. Firstly, a FLASH memory cell is programmed with a considerable drain-source current. As a result, in the event of simultaneous programming of all the cells of a word, a high current is collected by the select transistor of the source line. This current leads to an increase in the drain-source voltage of the select transistor, a corresponding reduction in the drain-source voltage of the floating-gate transistors, and an increase in the programming time. The cells of a single word must therefore be programmed individually, or jointly with cells belonging to other binary words (WO 98/33187). Furthermore, providing source line select transistors is not compatible with the channel erase method. In fact, as the erase voltage VER+ is, in this case, applied through the material forming the channel, providing source line select transistors does not prevent the voltage VER+ from reaching the sources of transistors and from creating an electric field leading to charges trapped in the floating gates being forced out.
Therefore, an object of the present invention is to provide a method for selectively erasing one page of FLASH memory that does not require providing source line select transistors.
Another object of the present invention is to provide a method for selectively erasing one page of FLASH memory that is compatible with the channel erase method.
Another object of the present invention is to provide a page-programmable FLASH memory that is protected against a possible alteration of the threshold voltage of its floating-gate transistors, due in particular to the implementation of a selective page-erase method according to the present invention.
Therefore, the present invention provides a method for logging data in a FLASH memory comprising at least one sector, wherein the erasing of a page from the memory comprises applying a negative erase voltage to the gates of the floating-gate transistors of the page to be erased, applying a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of the sector of the memory comprising the page to be erased, and applying a positive inhibit voltage to the gates of the transistors of at least one page of the memory that is not to be erased. The method comprises a step of controlling at least one page of the memory, comprising a first reading of the page by applying a first read voltage to the gates of the transistors of the page, a second reading of the page by applying a second read voltage to the gates of the transistors of the page, and reprogramming transistors if the two readings yield different results.
According to one embodiment, the second read voltage is higher than the first read voltage, the first read voltage corresponds to a normal read voltage used during phases of reading the memory, and the transistors are reprogrammed by using the data read by applying the first read voltage as reprogramming data.
According to one embodiment, the inhibit voltage is lower than the positive erase voltage.
According to one embodiment, the method comprises a step of providing voltage adapter circuits in the memory, each receiving a page select signal at input and delivering to the gates of the transistors of the corresponding page: a positive voltage, when the page select signal has a first value corresponding to the non-selection of the page and the memory is in erase mode or when the select signal has a second value corresponding to the selection of the page and the memory is not in erase mode, or a bias voltage lower than the positive voltage, when the select signal has the second value and the memory is in erase mode or when the select signal has the first value and the memory is not in erase mode.
According to one embodiment, the voltage adapter circuits receive: a bias voltage equal to the negative erase voltage and a positive voltage equal to the inhibit voltage during the erasing of a page, and a bias voltage equal to the ground potential and a positive voltage equal to a read voltage during the reading of a word in the memory.
According to one embodiment the method comprises, after each writing of a page in a sector of the memory, controlling K pages of the sector considered, K being strictly lower than the number of pages of the sector considered and at least equal to 1.
According to one embodiment, the control step is applied to at least one page of the memory located at an address read in a non-volatile counter formed by at least one row of floating-gate transistors.
According to one embodiment, the counter is incremented by one unit after the control of at least one page, by programming at least one floating-gate transistor of the counter without erasing the other transistors of the counter, the transistor programmed upon each new increment of the counter being the transistor following the transistor programmed upon the previous increment, according to a reading direction of the counter.
According to one embodiment, the counter comprises a plurality of words of increasing rank, and the reading in the counter of the address of at least one page to be controlled comprises the steps of reading the counter word by word until a word comprising a bit corresponding to an erased transistor is found, determining the most significant bits of the address of the page to be controlled using the rank, in the counter, of the first word found comprising a bit corresponding to an erased transistor, and determining the least significant bits of the address of the page to be controlled using the rank, in the first word found, of the first bit corresponding to an erased transistor.
According to one embodiment, the floating-gate transistors of the counter are arranged in a sector exclusively dedicated to the counter, such that programming voltages applied to floating-gate transistors of another sector of the memory are not passed onto the floating-gate transistors of the counter.
According to one embodiment, a page is controlled word by word and the control of a word comprises reading the word with the first read voltage, reading the word with the second read voltage, and reprogramming transistors if the two readings yield different results.
According to one embodiment, the positive erase voltage is applied to the source or drain electrodes of the floating-gate transistors through the material forming the channel of the transistors.
The present invention also relates to a page-erasable FLASH memory comprising a memory array comprising a plurality of pages each comprising floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, means for applying a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector comprising a page to be erased. The word line decoder comprises means for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased, the memory comprising means for controlling at least one page of the memory, arranged to carry out a first reading of the page by applying a first read voltage to the gates of the transistors of the page, carrying out a second reading of the page by applying a second read voltage to the gates of the transistors of the page, and reprogramming transistors of the page if the two readings yield different results.
According to one embodiment, the second read voltage is higher than the first read voltage, the first read voltage corresponds to a normal read voltage used during phases of reading the memory, and transistors are reprogrammed by using the data read by applying the first read voltage as reprogramming data.
According to one embodiment, the inhibit voltage delivered by the word line decoder is lower than the positive erase voltage.
According to one embodiment, the word line decoder comprises voltage adapter circuits receiving a page select signal at input and delivering to the gates of the transistors of the corresponding page: a positive voltage, when the select signal has a first value corresponding to the non-selection of the page and the memory is in erase mode or when the select signal has a second value corresponding to the selection of the page and the memory is not in erase mode, or a bias voltage lower than the positive voltage, when the select signal has the second value and the memory is in erase mode or when the select signal has the first value and the memory is not in erase mode.
According to one embodiment, the memory comprises means for supplying the voltage adapter circuits with: a bias voltage equal to the negative erase voltage and a positive voltage equal to the inhibit voltage during the erasing of a page, and a bias voltage equal to the ground potential and a positive voltage equal to a read voltage during the reading of a word in the memory.
According to one embodiment, the voltage adapter circuit comprises an output inverting stage receiving firstly the positive voltage and secondly the bias voltage, and a control stage of the inverting stage comprising an EXCLUSIVE OR logic function receiving the select signal and a signal having a determined value during the erasing of a page at input.
According to one embodiment, the control means are arranged for controlling, after each writing of a page in a sector of the memory, K pages of the sector considered, K being strictly lower than the number of pages of the sector considered and at least equal to 1.
According to one embodiment, the control means comprise a non-volatile counter formed by at least one row of floating-gate transistors, means for reading the address of at least one page to be controlled in the counter, and means for incrementing the counter after the control of at least one page.
According to one embodiment, the means for reading the address of at least one page to be controlled comprise means for reading the counter word by word and for searching for a word containing a bit corresponding to an erased transistor, means for delivering most significant bits of the address of the page to be controlled using the rank, in the counter, of the first word found containing a bit corresponding to an erased transistor, and means for calculating least significant bits of the address of the page to be controlled using the rank, in the first word found, of the first bit corresponding to an erased transistor.
According to one embodiment, the means for incrementing the counter are arranged to program at least one floating-gate transistor of the counter without erasing the other transistors of the counter, the transistor programmed upon each new increment being the transistor following the transistor programmed upon the previous increment, according to a reading direction of the counter.
According to one embodiment, the floating-gate transistors of the counter are arranged in a sector exclusively dedicated to the counter, such that programming voltages applied to floating-gate transistors of another sector of the memory are not passed onto the floating-gate transistors of the counter.
According to one embodiment, the means for controlling at least one page are arranged to control a page word by word, the control of a word comprising reading the word with the first read voltage, reading the word with the second read voltage, comparing the results of the two readings and reprogramming the transistors of the word if the two readings yield different results.
According to one embodiment, the positive erase voltage is applied to the source or drain electrodes of the floating-gate transistors through the material forming the channel of the transistors.